Removed text relocation code in OpenMax assembly files.
Chromium issue # 8061013
Tested with N-4. Related FFTs' SNR same as before.
R=rtoy@google.com
Review URL: https://webrtc-codereview.appspot.com/1687004
git-svn-id: http://webrtc.googlecode.com/svn/deps/third_party/openmax@4261 4adac7df-926f-26a2-2b94-8c16560cd09d
diff --git a/dl/sp/src/armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S b/dl/sp/src/armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S
index 3e36093..4447e76 100644
--- a/dl/sp/src/armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S
+++ b/dl/sp/src/armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S
@@ -173,19 +173,15 @@
#define dT0 D14.F32
#define dT1 D15.F32
-@// Define constants
- @ sqrt(1/2)
-ONEBYSQRT2: .float 0.7071067811865476e0
-
-
.MACRO FFTSTAGE scaled, inverse, name
@// Define stack arguments
@// Update pSubFFTSize and pSubFFTNum regs
@// subFFTSize = 1 for the first stage
+ MOVW t0, 0x04f3 @// Low half word of sqrt(1/2).
MOV subFFTSize,#8
- LDR t0,=ONEBYSQRT2
+ MOVT t0, 0x3f35 @// High half word of sqrt(1/2).
@// Note: setCount = subFFTNum/8 (reuse the grpSize reg for setCount)
LSR grpSize,subFFTNum,#3
@@ -285,7 +281,7 @@
@// finish first stage of 8 point FFT
VSUB qU7,qX3,qX7
- VLD1 dT0[0], [t0]
+ VMOV dT0[0], t0
@// finish second stage of 8 point FFT
diff --git a/dl/sp/src/armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S b/dl/sp/src/armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S
index 4c80b20..a5fb0e2 100644
--- a/dl/sp/src/armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S
+++ b/dl/sp/src/armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S
@@ -187,18 +187,16 @@
#define dT0 D14.S32
#define dT1 D15.S32
-@// Define constants
- .set ONEBYSQRT2, 0x5A82799A @// Q31 format
-
-
.MACRO FFTSTAGE scaled, inverse, name
@// Define stack arguments
@// Update pSubFFTSize and pSubFFTNum regs
- MOV subFFTSize,#8 @// subFFTSize = 1 for the first stage
- LDR t0,=ONEBYSQRT2 @// t0=(1/sqrt(2)) as Q31 value
-
+ MOVW t0, 0x799A @// Low half word of 1/sqrt(2) in Q31.
+ MOV subFFTSize,#8
+ MOVT t0, 0x5A82 @// High half word of 1/sqrt(2) in Q31.
+
+
@// Note: setCount = subFFTNum/8 (reuse the grpSize reg for setCount)
LSR grpSize,subFFTNum,#3
MOV subFFTNum,grpSize
diff --git a/dl/sp/src/omxSP_FFTFwd_RToCCS_F32_Sfs_s.S b/dl/sp/src/omxSP_FFTFwd_RToCCS_F32_Sfs_s.S
index 1389854..fda1ae4 100644
--- a/dl/sp/src/omxSP_FFTFwd_RToCCS_F32_Sfs_s.S
+++ b/dl/sp/src/omxSP_FFTFwd_RToCCS_F32_Sfs_s.S
@@ -128,8 +128,6 @@
#define half d0.f32
-HALF: .float 0.5
-
@// Allocate stack memory required by the function
@// Write function header
@@ -299,9 +297,7 @@
@// Process 4 elements at a time. E.g: F(1),F(2) and F(N/2-2),F(N/2-1)
@// since both of them require Z(1),Z(2) and Z(N/2-2),Z(N/2-1)
-
- LDR t0, =HALF
- VLD1 half[0], [t0]
+ VMOV half, #0.5
evenOddButterflyLoop:
